(1) Field of the Invention
This invention relates to a build-up layer packaging and a method thereof, and more particularly to a low coefficient of thermal expansion (CTE) build-up layer packaging formed by using co-fired ceramic technology.
(2) Description of Related Art
As the prosperity of the semiconductor fabrication technology, a central processing unit (CPU) characterized with small-size, multi-function, and high-speed becomes popular. Such CPU needs an increased number of input/output (I/O) contacts to transmit data for various functions, and is usually formed with arrayed I/O pads to increase I/O density (pitch≦200 μm). To deal with the arrayed I/O pads, a flip-chip packaging method, in which a die is connected to a packaging substrate by using bumps, is usually used.
FIG. 1 is a schematic view of a traditional flip-chip packaging. A core substrate 10 is provided as a main body to have an upper circuit layer 12 and a lower circuit layer 14 on opposing sides (upper side and lower side, respectively) by using a traditional build-up layer technology. A plurality of pins 16 is connected to the lower circuit layer 14 for plugging into the respective slots on a main board (not shown). A die 20 is flipped and placed on the upper circuit layer 12, and connects to the upper circuit layer 12 through a plurality of arrayed metal bumps 22 formed on a lower surface of the die 20. Therefore, a signal generated from the die 20 must pass through the bump 22, the upper circuit layer 12, a plated through hole (PTH) (not shown) in the core substrate 10, the lower circuit layer 14, and the pin 16 before reaching the main board.
It is noted that the core substrate 10 must have enough thickness to prevent circuit breakage in the upper circuit layer 12 and the lower circuit layer 14 mainly due to unexpected core substrate's torsion. Whereas the thickness of the core substrate 10 is increased to avoid possible breakage in the core substrate 10, some unwanted results such as thicker packaging, longer signal transmission distance from the die to the pin and so on can be raised. Moreover, as the thickness of the core substrate 10 is increased, the process of drilling PTH in the core substrate 10 becomes more difficult and thus limits the density of PTH. Therefore, the traditional flip-chip packaging of FIG. 1 now hits a bottleneck while the contemporary technology meets an increasing need in extending the I/O number and the density. To overcome the aforesaid bottleneck, a bumpless build-up layer packaging (BBUL) technology is introduced in time.
FIGS. 2A through 2F are schematic views of the BBUL packaging method. Firstly, as shown in FIG. 2A, a packaging substrate 100 is provided with a through hole 102. A temporal substrate 110 is formed under a bottom surface of the packaging substrate 100 so as to block a bottom end of the through hole 102a and thus to form a space with an upward opening for placing a die 200 therein. Referring to FIG. 2B, after the die 200 is placed into the through hole 102, the temporal substrate 110 is removed to expose the pads 202 on a lower surface of the die 200.
Thereafter, as shown in FIG. 2C, a dielectric layer 122 is formed on a common lower surface of the packaging substrate 100 and the die 200, and the pads 202 of the die 200 are also covered as shown. The dielectric layer 122 is then drilled by using a laser to form a plurality of openings 124 for exposing the pads 202. Afterward, as shown in FIG. 2D, a metal pattern 126 is formed on a lower surface of the dielectric layer 122 and fills the opening 124 (see FIG. 2C) to connect the pads 202. By repeating the steps of FIGS. 2C and 2D, the dielectric layers and the metal patterns are form alternatively to conclude a circuit layer 120 of FIG. 2E. Afterward, as shown in FIG. 2F, a solder mask (SM) 130 with a plurality of openings is formed on a lower surface of the circuit layer 120. Finally, the openings are then printed with solder 140 for further connecting a plurality of pins 150.
As mentioned, in the BBUL packaging method, the die 200 is placed and fixed in the packaging substrate 100, the lower surface of the die 200 and the packaging substrate 100 are applied with build-up layer technology to form the circuit layer 120, and then the pins 150 follows. Therefore, the signal generated in the die 200 only has to pass through the circuit layer 120 and the pin 150 before reaching the main board, and the thickness of the packaging and the energy dissipation during signal transmission are also reduced. It is calculated that, by compared to the traditional flip-chip packaging, the BBUL packaging reduces at least 30% of parasitic inductance, and saves at least 25% of power consumption during signal transmission in the packaging.
In addition, with a decrease of processor size and an increase of element density, an RC time delay effect resulted by the circuit inside the packaging becomes a main cause that affects the calculation speed of the processor. It is noted that the RC time delay of the packaging is a product of the resistance (R) of the metal patterns and the capacitance (C) of the dielectric layer between the metal patterns. Thus, there are two methods to minimize the RC time delay effect; in which one is to use low resistance metal materials, for example copper, to compose the metal pattern, and another is to use low dielectric parameter (K) materials to compose the dielectric layer.
It is well known in the art that an advanced low K material is more brittle than other traditional dielectric materials. In a traditional flip-chip packaging, which uses bumps as electric connections between a die and a packaging substrate, the dielectric layer covering the die suffers a pressure from the bump. If a brittle low K material is used to form the dielectric layer, the surface layers of the die will be vulnerable to break the circuit therein and thus decrease the yield. In the BBUL packaging of FIG. 2F, the die 200 is placed and fixed inside the packaging substrate 100, and the circuit layer 120 is directly formed on the lower surface of the die 200 and, therefore, no bumps are needed in such a structure. So, upon such an arrangement of the bumpless packaging, damage causes by using low K material bumps can be prevented.
However, in the traditional BBUL packaging, the die and the packaging substrate are composed of materials with a significant difference in coefficient of thermal expansion (CTE). For example, a typical packaging substrate is usually formed by an organic material having a CTE around 20 ppm/° C., while a typical silicon die has a CTE of 4.5 ppm/° C. The difference of CTEs between the packaging substrate and the die is estimated up to 15.5 ppm/° C. Therefore, upon a thermal stress in any thermal cycle in the packaging process or upon a residue stress existing between the die and the packaging substrate by a dimensional mismatch during manufacturing, the connection between the die and the packaging substrate may be accidentally broken and fail the packaging.
Moreover, as shown in FIGS. 2C through 2E, in the BBUL packaging process, a laser drilling step and a build-up layer step are carried out after the die is placed and fixed inside the substrate. Therefore, any defect in such laser drilling and build-up layer steps may eventually fail the packaging and thus reduce the yield. Definitely, the die inside the substrate in a failed packaging is impossible to be used again.